News
News
2012/02/02
Stellenausschreibung
Wiss. Mitarbeiters/Mitarbeiterin mit Universitätsabschluss in Maschinenbau, Verfahrenstechnik, Physik, Elektrotechnik, Chemie
Im Institut für Druckmaschinen und Druckverfahren des Fachbereichs Maschinenbau ist ab sofort die Stelle eines/einer Wiss. Mitarbeiters/Mitarbeiterin mit Universitätsabschluss in Maschinenbau, Verfahrenstechnik, Physik, Elektrotechnik, Chemie in einem zunächst auf 3 Jahre befristeten Arbeitsverhältnis zu besetzen.
weiter
2011/10/18
Open Thesis:
Design and Implementation of Wallace-TreeMultiplier.
A 32-bit Wallace-Tree Digital Multiplier will be designed and simulated by using VHDL or Verilog HDL. The Multiplier is one of important components that will be used to implement a high-performance pipeline floating-point (FP) multiplier. The critical path of the FP multiplier is located in the multiplication stage. There are some techniques that can be used to realize a digital multiplier suchas Wallace-Tree method. This method is famous and enables us to pipeline the multiplication process in order to shorten the critical path. The performance and logicarea of the Wallace-Tree Multiplier will be analysed by using Design Vision tool fromSynopsys.
2011/10/18
Open Thesis:
Modelling and Simulation of heterogeneous systems in energy harvesting applications.
Heterogeneous subsystems such as ADC, Low-Pass Filter, Digital Circuit Core, DAC, Sample-Hold circuit, PWM Circuit, etc will be designed by using VHDL-AMS (Analog/Mixed-Signal). VHDL-AMS is an advanced hardware description language standardized by IEEE, which can be used to model heterogeneous systems such as difference and differential equations, linear and non linear system models, analog and digital circuits, etc. Each subsystem will be independently modelled as a modular cell or component. The interactions between the components will be simulated and observed by using AMS Designer tools from Cadence. In this topic, Student who has interest will gain an advanced skill to model heterogeneous systems and to simulate mixed analog-digital systems.
2011/10/18
Open Thesis:
Design and Implementation of Floating-Point Square Root, Division, Logarithmic and Exponent Functions.
Beside basic operations such as adding, subtracting and multiplication, there are also arithmetic operations such as square root, division, logarithmic, exponent function, etc, which are used to perform computing algorithms in a scientific computing application. There are some methods that can be used to implement the operations such as CORDIC (COordinateRotation DIgitalComputer) method. A challenge to implement an IP core of the functions by using VHDL or Verilog HDL based on floating-point data format is proposed. Student who has interest can select one of the function units, which he/she prefers to design. The performance and logic areaof the selected function will be analysed by using Design Visiontool from Synopsys.
2011/10/18
Open Thesis:
Analog/Mixed-Signal IP Cores Design: CMOS multiplier, subtractor, low pass filter, ADC.
In the frame of the Project LOEWE-AdRIA (Adaptronik-Research, Innovation, Application), we are offering a Bachelor/Master Thesis or (Studien-/Diplomarbeit) about IP core design of an analog multiplier, subtractor and low pass filter, which are used in an ambient energy harvesting system. The cores will be integrated together with a PWM-Circuit for a solar-based and/or a TEG-based energy-harvesting system, which is an important part for battery-powered wireless sensor network applications.
2011/10/18
Open Thesis:
Floating-Point to DAC-Input Signal Converter and ADC Output to Floating-Point Converter Circuit.
Converter circuits will be designed and implemented by using VHDL or Verilog HDL. One converter is designed to transform the output signals of a floating-point digital signal processor into binary signals that can be read by a DAC circuit. The other other converter is designed to transform the output signals of an ADC circuit into floating-point binary signals that can be processed further by a floating-point digital signal processor. The format of the floating-point data is in accordance with IEEE Std 754-2008, i.e. 32-bit (single precision) with 1 sign bit + 8 exponent bits + 23 mantissa bits. A simple method such as two-point regression method can be used to realize an IP core of the converters. The converters are important parts of a floating-point-based application-specific processor for embedded applications. Student who has interest can select one of the converter circuits, which he/she prefers to design.
2011/10/18
Open Thesis:
Modelling and Simulation of heterogeneous subsystems in adaptronic applications.
Heterogeneous subsystems such as Laplace and Z-transfer functions, ADC, Low-Pass Filter, Digital Circuit Core, DAC, Sample-Hold circuit, Power Amplifier circuit, etc will be modelled by using VHDL-AMS (Analog/Mixed-Signal). VHDL-AMS is an advanced hardware description language standardized by IEEE, which can be used to model heterogeneous systems such as difference and differential equations, linear and non linear system models, analog and digital circuits, etc. Each subsystem will be independently modelled as a modular cell or component. The interactions between the components will be simulated and observed by using AMS Designer tools from Cadence. In this topic, Student who has interest will gain an advanced skill to model heterogeneous systems and to simulate mixed analog-digital systems.
2011/09/19
Open Study / Diploma / Bachelor / Master Theses
Effect of control signals on control stability
Background: In a joint research project with the Gesellschaft für Schwerionenforschung (GSI), we are working on distributed closed-loop real-time control systems for particle accelerators. A system-level model of a synchrotron and some of its control systems has already been developed.
Objectives: Using the existing model, different input functions are to be compared to each other. Metrics are to be defined which should express how easy or difficult it is for the control system to follow the input function.
Prerequisites: No particular previous knowledge is required.
Contact: Christopher Spies
2011/09/19
Open Study / Diploma / Bachelor / Master Theses
Design alternatives for particle accelerator control systems
Background: In a joint research project with the Gesellschaft für Schwerionenforschung (GSI), we are working on distributed closed-loop real-time control systems for particle accelerators. A system-level model of a synchrotron and some of its control systems has already been developed.
Objectives: Using the existing model, different design alternatives are to be simulated and compared to each other.
Prerequisites: No particular previous knowledge is required.
Contact: Christopher Spies
2011/08/10
Open Study / Diploma / Bachelor / Master Theses
Comparative Analysis of Directed Design Space Search Algorithms
Background: Engineers are frequently confronted with the problem of having to optimize the design parameters of a system according to a quality function that can be evaluated numerically but not analytically. This is especially true in model-based design and optimization approaches. Since the optimum can't be found analytically, one has to resort to trying several candidate solutions and comparing them to each other.
Objectives: Directed design space search algorithms (e. g. Hill Climbing or genetic algorithms) are better than random (Monte-Carlo) strategies. Different algorithms are to be implemented and compared to each other with respect to their ability of finding good solutions and the number of steps required.
Prerequisites: Some programming experience (preferrably in Java) and a general interest in optimization techniques are required.
Kontakt: Christopher Spies