Topics of interest include (but are not limited to):
- New paradigms for reconfigurable and communication-centric computing
- Reconfigurable and adaptive embedded SoCs
- Communication-centric design techniques at different abstraction levels
- On-chip communication architectures
- Low power design of reconfigurable and multiprocessor SoCs
- Communication-aware multiprocessor embedded systems
- OS and middleware for reconfigurable and multicore SoCs
- Specification languages and design methodologies
- Verification and evaluation techniques
- Industrial case studies
Special Sessions:
Special Sessions will be organized on several hot topics, as for example:
Architecture, programming and run-time techniques for heterogeneous MPSoCs
Organization : Luciano Ost, LIRMM (FR):
- Efficient mapping/scheduling
- Programmability of Heterogeneous MPSoC
- Virtualization techniques and platform clustering
- Multi-domain development methodology
- Power-efficient for Heterogeneous Platform
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Reconfigurable Systems for Security Applications
Organization : Marc Stöttinger, Nanyang Technological University (SG)
- Efficient and High Performance Implementation for FPGA-based Crypto Systems
- IP-core Rights Management and Bitstream Encryption
- Side Channel and Fault Attack Resistant FPGA Implementations
- Design Flow for FPGA-based Secure Systems
- Hardware Trojan Design and Detection on Reconfigurable Systems
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Architecture and development for application specific processors
Organization : Michael Hübner, Uni Bochum (DE) :
- Architecture description languages
- Compiler
- Processor Microarchitecture
- Instruction Set Definition
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Algorithms for online synthesis
Organization : Christian Hochberger and Andreas Koch, TU Darmstadt (DE):
- Low complexity algorithms for demand driven online synthesis
Reconfigurable Systems can change their characteristics at runtime. In order to truly exploit that feature, it will be necessary to synthesize configurations for the reconfigurable part also at runtime. This approach is sometimes called online-synthesis. Unfortunately, many tasks during synthesis have exponential runtime and are therefore not suitable for online-synthesis. Thus, one tries to trade result quality for algorithm runtime in these algorithms. Submissions are welcome that either present new approaches or that try to tweak existing algorithms for this purpose.
Important Dates :
Submission Deadline (regular papers) : 10th May 2013, 23:59 CEST (extended deadline)
Submission Deadline (special sessions) : 17th May 2013, 23:59 CEST (extended deadline)
Notification of Acceptance : 31st May 2013
Camera-ready Due : 14th June 2013
All accepted papers will be published in IEEE Xplore, and the authors of the best papers will be invited to submit an extended version of their contribution in ACM Transactions on Reconfigurable Technology and Systems (ACM TRETS)