Program

Keynote 1

Wednesday July 10th 2013, 09:15 – 10:15

Frederic Pétrot(TIMA Lab, Grenoble, France)
Some design issues for 3D Network-on-Chip: from circuits to systems

Abstract :

The emergence of the NoC concept in the early 2000 has led to a drastic change in considering on-chip interconnect. This has led to a large body of research since, and several practical multiprocessor systems-on-chip that rely on this technology have been fabricated lately. The recent introduction of technologies making use of the third dimension introduces new issues at all levels of the design.

This talk will focus on some of these issues, namely circuit level techniques for communication among IPs which have different timing behaviors, circuit and system strategies for limiting of the number of vertical links, system approach for routing packets in 3 dimensions within non-fully connected networks, …

Petrot

Biography of the Speaker

Frédéric Pétrot received the DEA (master) and PhD degree in Computer Science from Université Pierre et Marie Curie (Paris VI), Paris, France, in respectively 1990 and 1994. From 1995 to 2004, he was assistant professor, and contributed actively to the Alliance VLSI CAD System and the Disydent ESL environment. F. Pétrot joined TIMA in September 2004, and holds a professor position at the Grenoble Institute of Technology, France, where, since 2007, he heads the System Level Synthesis group. His main research interests are in system level design of integrated systems, and include computer aided design of digital system, architecture and software for homogeneous and heterogeneous multiprocessor systems on chip.

Keynote 2

Thursday July 11th 2013, 08:45 – 09:45

William Fornaciari (Politecnico di Milano)
Targeting Applications and Platform “Variability” Challenges: the BarbequeRTRM approach

Abstract :

These years are characterized by the presence of a variety of possible computing platforms ranging from symmetric to heterogeneous architectures, multi-core and many-core. Meanwhile we are also noticing a convergence of application fields which are more and more overlapped, especially considering multimedia processing. Among the main issues to be solved, to effectively exploit computational platform capabilities while matching time varying applications requirements, some are related to programming models support and optimal resources management. A challenging problem is the definition of advanced resources management techniques which provides near-optimal resources allocation on systems where a mixed workload of different applications are competing on the usage of a relatively limited amount of resources, all that considering both time varying application-specific as well as system-wide optimization goals.

In that scenario, especially in the case of high-end embedded systems, it is no longer possible to fully optimize the computing platform and application configuration only at design time, but some degree of adaptability and fine-tuning is mandatory at run-time as well.

This talk will focus on an emerging class of platforms exploiting the computational capability of a huge amount of cores, possibly clustered, when several complex applications have to run concurrently under QoS requirements which have to be targeted while still pursuing a system-wide optimization as well. As an example of a possible solution, it will present the approach inspiring the BarbequeRTRM, a Run-Time Resource Management framework which aims to provide:

  • joint design/run-time application optimization strategy
  • an straightforward integration with system-wide run-time resource management
  • optimal management of multi-cores real architectures, e.g. STHORM platform (low-power embedded 64 core by STMicroelectronics), NUMA architectures and multi-GPGUP systems
  • easy access to instrumentation and monitoring supports for system and application optimizations
  • energy and power optimizations under QoS constraints
  • stability and robustness enforcement under mixed workloads conditions

The framework has been designed with the aim to pursue the highest possible level of portability, through a user-space implementation. Moreover, thanks to its modularity, it also easy to extend and adapt by implementing ad-hoc resource management policies.

A library (RTLib) is also provided to developers, to support the design and implementation of run-time adaptive applications, by exporting a well-defined Abstract Execution Model (AEM). This model straightly abstracts the execution model of most multimedia applications, which are the most critical from the resource management point of view in high-end embedded systems.

Overall, the framework outlines a hierarchical and distributed control of resource assignment, driven by multi-objective optimization policies, taking into account application-specific requirements along with non-functional system-wide objectives (e.g., overhead minimization, power saving, thermal hot-spot avoidance).

The BarbequeRTRM framework is part of the BOSP open-source project: http://bosp.dei.polimi.it

Biography of the Speaker

William Fornaciari is professor at the Politecnico di Milano, Italy, Dipartimento di Elettronica, Informazione e Bioingegneria and he also worked also as a consultant for the technology transfer of POLIMI for 20 years. In FP7 he has been Project Technical Manager of the 2PARMA project and contributed to the projects COMPLEX and SMECY. Starting from fall 2013 he will be Project Coordinator of the HARPA project and WP leader of the CONTREX project.

His current research interests include embedded systems design methodologies, energy-aware design of sw and hw, runtime management of resources, reconfigurable computing and wireless sensor networks, design and optimization of multi-core systems, reliability of multi-core systems and NoC. He collected four best paper awards, one certification of appreciation from IEEE and holds two international patents on low power design solutions. In 2013 he funded the startup “IBT Solutions”, focusing on the design of embedded systems.

Keynote 3

Thursday July 11th 2013, 09:45 – 10:30

Jean-Philippe Diguet (Lab-STICC, CNRS, UMR 6285)
Template-based design and programming of self-adaptive architectures for embedded systems

Abstract :

In the domain of embedded systems, reconfigurable architectures are an opportunity to dynamically specialize SoC according to context-dependent application needs. Many studies have shown the benefit of such a technology which allows greater flexibility, performances and cost reductions. However the design of complex architectures, the lack of programmability models and systematic decision-making for self-reconfiguration seriously hamper the adoption of such FPGA-based solutions.

This talks presents a synthesis of the team MOCS approach to come up with these issues. The proposed solution first relies on flexible architecture template, on HW/SW libraries of standard functions that can be generated by means of HLS tools in the design loop and programmed with hardware independent API. The second point to be presented is the close-loop decision-making approach that enables performing on-the-fly hardware/software reconfiguration, according to application requirements.

Diguet

Biography of the Speaker

Jean-Philippe Diguet has obtained his Ph.D degree from Rennes University (France) in 1996. In 1997, he has been a visitor researcher at IMEC (Belgium). He has been an associated professor at UBS University (France) from 1998 until 2002. In 2003 he co-funded a SME in the area of wireless embedded systems. Since 2004 he is a CNRS researcher at Lab-STICC (France), where is heading the MOCS team. His work focuses on design methodologies and architectures of embedded systems. It includes computer-aided design tools (CAD) for behavioural synthesis of heterogeneous multiprocessor SoC, self-adaptive Network-on-Chip and model-based power and energy estimation of complete embedded systems. Another part of his work targets on programming environment for self-adaptive hardware and software architectures, which implement autonomous configuration decision within reconfigurable SoC. Finally, he is now exploring some new distributed networked embedded systems for different application domains such as body area network, remote healthcare and smart sailing boats.

Keynote 4

Friday July 12th 2013, 08:45 – 09:30

Norbert Wehn (TU Kaiserslautern)
Efficiency Metrics and Bandwidth– A Memory Perspective

Abstract :

The race for increasing computing performance implied a dramatic increase in power which represents the main wall for further increase in computing. The “multi-core revolution” has shown a way out. Thus, today’s state-of-the-art architectures in embedded computing are based on heterogeneous multi-core architectures with application specific optimized accelerators. Unfortunately the immense computing power of such multi-core architectures brings as negative effect an increased demand on bandwidth and memory, denoted as bandwidth and memory walls. In this talk we will discuss two topics strongly related to the memory and bandwidth wall. First, the impact of memories and data transfers on metrics to compare different algorithms and implementations in the context of wireless baseband processing architectures. Second, the design space and potential of 3D DRAM architectures and multi-channel DRAM controllers.

Wehn

Biography of the Speaker

Norbert Wehn holds the chair for Microlectronic Systems Design in the department of Electrical Engineering and Information Technology at the University of Kaiserslautern. He has published more than 200 articles in conferences and journals in various fields of microelectronic systems design and holds several patents. He is chairman of the European Design Automation Association, chairman of the Research Center “Ambient Systems” TU Kaiserslautern, associate editor of various journals and a member of several scientific advisory boards. In 2003 he served as program chair for the DATE 2003 conference and as general chair for DATE 2005, respectively. His special research interests are VLSI-achitectures for mobile communication, forward error correction techniques, low-power, advanced SoC architectures, and reliability issues in SoC.

Keynote 5

Friday July 12th 2013, 09:30 – 10:15

Christoph Grimm (TU Kaiserslautern)
Design of Energy-Aware Cyber-Physical Systems

Abstract :

Cyber-physical systems combine embedded systems with information systems.
Energy-aware design is a particular challenge, because the embedded systems are distributed, and often autonomous operation for years is required.
To achieve such run-times comprehensive design methods are required that enable optimization of architecture, communication stack, and application.

The talk will give an overview of methods for modeling, simulation, and power profiling, using tire pressure metering as an industrial case study.
As an outcome of architecture exploration, a reconfigurable architecture is proposed that combines flexibility with very little standby power.

Grimm

Biography of the Speaker

Christoph Grimm is working on modeling and design of analog/mixed-signal systems with particular focus on modeling languages.
He contributed to standardization of VHDL-AMS and to SystemC AMS where he serves as a vice-chair of Accellera's AMS WG, and has co-authored the language reference manual and the user's guide.
He received a diploma in electrical engineering from TU Darmstadt (1994) and a Ph.D. from Frankfurt University (1999). He has been working as full professor of Embedded Systems at Vienna University of Technology (2006-2012).
Since 2012 he is full professor for design of Cyber-Physical Systems at Kaiserslautern University of Technology.