Studentische Arbeiten
Offene Studien- & Diplomarbeiten, Bachelor- & Master-Theses
18.10.2011
Offene Studien-, Bachelor-, Master-, Diplomarbeit
Design and Implementation of Wallace-TreeMultiplier.
A 32-bit Wallace-Tree Digital Multiplier will be designed and simulated by using VHDL or Verilog HDL. The Multiplier is one of important components that will be used to implement a high-performance pipeline floating-point (FP) multiplier. The critical path of the FP multiplier is located in the multiplication stage. There are some techniques that can be used to realize a digital multiplier suchas Wallace-Tree method. This method is famous and enables us to pipeline the multiplication process in order to shorten the critical path. The performance and logicarea of the Wallace-Tree Multiplier will be analysed by using Design Vision tool fromSynopsys.
18.10.2011
Offene Studien-, Bachelor-, Master-, Diplomarbeit
Modelling and Simulation of heterogeneous systems in energy harvesting applications.
Heterogeneous subsystems such as ADC, Low-Pass Filter, Digital Circuit Core, DAC, Sample-Hold circuit, PWM Circuit, etc will be designed by using VHDL-AMS (Analog/Mixed-Signal). VHDL-AMS is an advanced hardware description language standardized by IEEE, which can be used to model heterogeneous systems such as difference and differential equations, linear and non linear system models, analog and digital circuits, etc. Each subsystem will be independently modelled as a modular cell or component. The interactions between the components will be simulated and observed by using AMS Designer tools from Cadence. In this topic, Student who has interest will gain an advanced skill to model heterogeneous systems and to simulate mixed analog-digital systems.
18.10.2011
Offene Studien-, Bachelor-, Master-, Diplomarbeit
Design and Implementation of Floating-Point Square Root, Division, Logarithmic and Exponent Functions.
Beside basic operations such as adding, subtracting and multiplication, there are also arithmetic operations such as square root, division, logarithmic, exponent function, etc, which are used to perform computing algorithms in a scientific computing application. There are some methods that can be used to implement the operations such as CORDIC (COordinateRotation DIgitalComputer) method. A challenge to implement an IP core of the functions by using VHDL or Verilog HDL based on floating-point data format is proposed. Student who has interest can select one of the function units, which he/she prefers to design. The performance and logic areaof the selected function will be analysed by using Design Visiontool from Synopsys.
18.10.2011
Offene Studien-, Bachelor-, Master-, Diplomarbeit
Analog/Mixed-Signal IP Cores Design: CMOS multiplier, subtractor, low pass filter, ADC.
In the frame of the Project LOEWE-AdRIA (Adaptronik-Research, Innovation, Application), we are offering a Bachelor/Master Thesis or (Studien-/Diplomarbeit) about IP core design of an analog multiplier, subtractor and low pass filter, which are used in an ambient energy harvesting system. The cores will be integrated together with a PWM-Circuit for a solar-based and/or a TEG-based energy-harvesting system, which is an important part for battery-powered wireless sensor network applications.
18.10.2011
Offene Studien-, Bachelor-, Master-, Diplomarbeit
Floating-Point to DAC-Input Signal Converter and ADC Output to Floating-Point Converter Circuit.
Converter circuits will be designed and implemented by using VHDL or Verilog HDL. One converter is designed to transform the output signals of a floating-point digital signal processor into binary signals that can be read by a DAC circuit. The other other converter is designed to transform the output signals of an ADC circuit into floating-point binary signals that can be processed further by a floating-point digital signal processor. The format of the floating-point data is in accordance with IEEE Std 754-2008, i.e. 32-bit (single precision) with 1 sign bit + 8 exponent bits + 23 mantissa bits. A simple method such as two-point regression method can be used to realize an IP core of the converters. The converters are important parts of a floating-point-based application-specific processor for embedded applications. Student who has interest can select one of the converter circuits, which he/she prefers to design.
18.10.2011
Offene Studien-, Bachelor-, Master-, Diplomarbeit
Modelling and Simulation of heterogeneous subsystems in adaptronic applications.
Heterogeneous subsystems such as Laplace and Z-transfer functions, ADC, Low-Pass Filter, Digital Circuit Core, DAC, Sample-Hold circuit, Power Amplifier circuit, etc will be modelled by using VHDL-AMS (Analog/Mixed-Signal). VHDL-AMS is an advanced hardware description language standardized by IEEE, which can be used to model heterogeneous systems such as difference and differential equations, linear and non linear system models, analog and digital circuits, etc. Each subsystem will be independently modelled as a modular cell or component. The interactions between the components will be simulated and observed by using AMS Designer tools from Cadence. In this topic, Student who has interest will gain an advanced skill to model heterogeneous systems and to simulate mixed analog-digital systems.
19.09.2011
Offene Studien- & Diplomarbeiten, Bachelor- & Master Theses
Einfluss von Steuersignalen auf die Stabilität eines Regelsystems
Hintergrund: In einem gemeinsamen Forschungsprogramm mit der Gesellschaft für Schwerionenforschung (GSI), arbeiten wir an verteilten Echtzeit-Regelsystemen für Teilchenbeschleuniger. Ein Simulationsmodell eines Synchrotrons und einiger relevanter Regelsysteme wurde in unserer Forschungsgruppe bereits entwickelt.
Ziele der Arbeit: Es soll untersucht werden, wie die Wahl der Eingangsgrößen (der Ansteuerung) die Stabilität der Regelsysteme beeinflusst. Darauf aufbauend sollen Metriken definiert werden, die angeben, wie schwierig es für das Regelsystem ist, der Ansteuerung zu folgen.
Voraussetzungen: Es wird kein besonderes Vorwissen vorausgesetzt.
Kontakt: Christopher Spies
19.09.2011
Offene Studien- & Diplomarbeiten, Bachelor- & Master-Theses
Entwurfsalternativen für Beschleuniger-Regelsysteme
Hintergrund: In einem gemeinsamen Forschungsprogramm mit der Gesellschaft für Schwerionenforschung (GSI), arbeiten wir an verteilten Echtzeit-Regelsystemen für Teilchenbeschleuniger. Ein Simulationsmodell eines Synchrotrons und einiger relevanter Regelsysteme wurde in unserer Forschungsgruppe bereits entwickelt.
Ziele der Arbeit: Mit Hilfe des existierenden Modells sollen verschiedene Entwurfsalternativen simuliert und miteinander verglichen werden.
Voraussetzungen: Es wird kein besonderes Vorwissen vorausgesetzt.
Kontakt: Christopher Spies
10.08.2011
Offene Studien- & Diplomarbeiten, Bachelor- & Master-Theses
Vergleich gerichteter Optimierungsalgorithmen
Hintergrund: Häufig stehen Ingenieure vor dem Problem, die Parameter eines Systems anhand einer zwar numerisch berechenbaren, aber nicht analytisch lösbaren Gütefunktion optimieren zu müssen. Das ist vor allem bei modellbasierten Entwurfs- und Optimierungsmethoden der Fall. Da das Optimum der Gütefunktion in diesen Fällen nicht analytisch bestimmbar ist, bleibt nur das Ausprobieren verschiedener möglicher Lösungen und deren Vergleich untereinander.
Ziele der Arbeit: Besser als ein zufälliges Ausprobieren von Lösungen (Monte-Carlo-Ansatz) sind gerichtete Optimierungsalgorithmen, beispielsweise Hill Climbing oder genetische Algorithmen. Verschiedene Algorithmen sollen implementiert und miteinander verglichen werden. Kriterien sind dabei einerseits das Auffinden einer guten Lösung, andererseits die Anzahl der dazu erforderlichen Schritte.
Voraussetzungen: Programmierkenntnisse, vorzugsweise in Java, und grundsätzliches Interesse an Optimierungsverfahren sind erforderlich.
Kontakt: Christopher Spies