Wissenschaftliche und Berufliche Ausbildung:

1999 – 2003 Bachelor in Computer Science at the Catholic University of Rio Grande do Sul, Brazil

2004 – 2005 Master in Computer Science at the Catholic University of Rio Grande do Sul, Brazil

Since 2007 Promotion und Wissenschaftlicher Mitarbeiter am Fachgebiet Mikroelektronische Systeme, Technische Universität Darmstadt

Forschungs- und Arbeitsbereiche:

Reconfigurable Systems

Networks-on-Chip

Veröffentlichungen:

MÖLLER, Leandro Heleno; JESUS, Hélio Vieira; MORAES, Fernando Gehm; INDRUSIAK, Leandro Soares; HOLLSTEIN, Thomas; GLESNER, Manfred. Graphical Interface for Debugging RTL Networks-on-Chip. In: BEC (12th Biennial Baltic Electronics Conference), 2010, Tallinn, Estonia, p. 181-184.

MÖLLER, Leandro Heleno; FISCHER, Peter; MORAES, Fernando Gehm; INDRUSIAK, Leandro Soares; GLESNER, Manfred. Improving QoS of Multi-Layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers. In: FPL, 2010, Milan, Italy, p. 229-233.

MÖLLER, Leandro Heleno; RODRIGUES, André; MORAES, Fernando Gehm; INDRUSIAK, Leandro Soares; GLESNER, Manfred. Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors. In: ReCoSoC, 2010, Karlsruhe, Germany, p. 7-12.

INDRUSIAK, Leandro Soares; OST, Luciano; MORAES, Fernando Gehm; MAATTA, Sanna; NURMI, Jari; MÖLLER, Leandro Heleno; GLESNER, Manfred. Evaluating the Impact of Communication Latency on Applications Running Over On-Chip Multiprocessing Platforms: a Layered Approach. In: INDIN, 2010, Osaka, Japan, p. 148-153.

MAATTA, Sanna; MÖLLER, Leandro Heleno; INDRUSIAK, Leandro Soares; OST, Luciano; GLESNER, Manfred; NURMI, Jari; MORAES, Fernando Gehm. Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms. IJERTCS (International Journal of Embedded and Real-Time Communication Systems), 2010, vol. 1, n. 1, pp. 86-101.

MÖLLER, Leandro Heleno; INDRUSIAK, Leandro Soares; GLESNER, Manfred. NoCScope: A Graphical Interface to Improve Networks-on-Chip Monitoring and Design Space Exploration. In: IDT (International Design and Test Workshop), 2009, Riyadh, Saudi Arabia, pp. 1-6.

YU, Haile; LEONG, Philip H. W; HINKELMANN, Heiko; MÖLLER, Leandro Heleno; GLESNER, Manfred. Towards a Unique FPGA-Based Identification Circuit Using Process Variations. In: FPL, 2009, Prague, Czech Republic, p. 397-402.

MAATTA, Sanna; INDRUSIAK, Leandro Soares; OST, Luciano; MÖLLER, Leandro Heleno; GLESNER, Manfred; NURMI, Jari; MORAES, Fernando Gehm. Characterizing Embedded Applications using a UML Profile. In: SoC, 2009, Tampere, Finland, p. 172-175.

MAATTA, Sanna; INDRUSIAK, Leandro Soares; OST, Luciano; MÖLLER, Leandro Heleno; NURMI, Jari; GLESNER, Manfred; MORAES, Fernando Gehm. Validation of Executable Application Models Mapped onto Network-on-Chip Platforms. In: SIES, 2008, Montpellier, France, p. 118-125.

OST, Luciano; MORAES, Fernando Gehm; MÖLLER, Leandro Heleno; INDRUSIAK, Leandro Soares; GLESNER, Manfred; MAATTA, Sanna; NURMI, Jari. A Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip. In: SBCCI, 2008, Gramado, Brazil, p. 170-175.

INDRUSIAK, Leandro Soares; OST, Luciano; MÖLLER, Leandro Heleno; MORAES, Fernando Gehm; GLESNER, Manfred. Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. In: ISVLSI, 2008, Montpellier, France, p. 491-494.

VARYANI, Sameer; INDRUSIAK, Leandro Soares; LUI, Tianlun; OST, Luciano; MÖLLER, Leandro Heleno; GLESNER, Manfred. Experimental Review of Task Mapping Algorithms for NoC-based Multiprocessor Systems-on-Chip. In: ReCoSoC, 2008, Barcelona, Spain.

MÖLLER, Leandro Heleno; GREHS, Ismael Augusto; CARVALHO, Ewerson Luiz de Souza; SOARES, Rafael; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable System. In: ReCoSoC, 2007, Montpellier, France, p. 23-30.

MÖLLER, Leandro Heleno; GREHS, Ismael Augusto; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. Reconfigurable Systems Enabled by a Network-on-Chip. In: FPL, 2006, Madrid, Spain, p. 1042-1046.

MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; MORAES, Fernando Gehm. Redes Intra-chip: Projeto da Rede Hermes. Chapter Book. In: Ricardo Reis; Sandro Sawicki; Rafael Santos. (Org.). Advanced Topics on Microelectronics. Porto Alegre, Brazil: Doravante Publishers, 2006, p. 121-144 (in portuguese).

MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. A Multiprocessing System Enabled by a Network on Chip. In: DATE, 2005, Munique, Germany, p. 502-507.

MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MÖLLER, Leandro Heleno; BRIÃO, Eduardo Wenzel; CARVALHO, Ewerson Luiz de Souza. Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements and Tools. Chapter Book. In: LYSAGHT, Patrick; ROSENSTIEL, Wolfgang. (Org.). New Algorithms, Architectures and Applications for Reconfigurable Computing. New York, United States, 2005, p. 157-170.

MÖLLER, Leandro Heleno; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Processadores Reconfiguráveis: Estado da Arte. In: IBERCHIP, 2005, Salvador, Brazil, p. 110-113 (in portuguese).

MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm; BRIÃO, Eduardo Wenzel; CARVALHO, Ewerson Luiz de Souza; CAMOZZATO, Daniel. FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. In: FPL, 2004, Antwerp, Belgium, p. 1042-1046.

MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano. HERMES: An Infrastructure for Low Area Overhead Packet-Switching Networks on Chip. Integration The VLSI Journal, 2004, v. 38, n. 1, p. 69-93.

PALMA, José Carlos Sant'anna; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Core Communication Interface for FPGAs. JICS (Journal of Integrated Circuits and Systems), v. 1, n. 1, p. 44-51, 2004.

BRIÃO, Eduardo Wenzel; CARVALHO, Ewerson Luiz de Souza; MÖLLER, Leandro Heleno; CAMOZZATO, Daniel; CALAZANS, Ney Laert Vilar; MORAES, Fernando Gehm. A Generic Model of Embedded System to Enable Dynamic Self-Reconfigurable Applications. In: SIM, 2004, São Miguel das Missões, Brazil, p. 98-104.

CARVALHO, Ewerson Luiz de Souza; BRIÃO, Eduardo Wenzel; MÖLLER, Leandro Heleno; MÖLLER, Frederico Bartz; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Controlling Configurations on Dynamic Reconfigurable Systems. In: SIM, 2004, São Miguel das Missões, Brazil, p. 114-119.

MORAES, Fernando Gehm; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano Copello; CALAZANS, Ney Laert Vilar. Networks on Chip: Architecture and Prototyping. In: SIM, 2003, Novo Hamburgo, Brazil.

MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; MORAES, Fernando Gehm. Desenvolvimento de um Sistema Multiprocessado para Dispositivos FPGAs. In: IBERCHIP, 2003, Havana, Cuba (in portuguese).

MÖLLER, Leandro Heleno; MELLO, Aline Vieira de. „Multiprocessed Architectures in SoCs: a Trade-off Between Performance and Area“, 2003, Porto Alegre, Brazil, 120 pp. (BSc Thesis, in portuguese).

MESQUITA, Daniel; MORAES, Fernando Gehm; PALMA, José Carlos Sant'anna; MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar. Remote and Partial Reconfiguration of FPGAs: Tools and Trends. In: IPDPS, 2003, Nice, France, 8 pp.

MORAES, Fernando Gehm; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; OST, Luciano; CALAZANS, Ney Laert Vilar. A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. In: VLSI SOC, 2003, Darmstadt, Germany, p. 318-323.

MORAES, Fernando Gehm; MESQUITA, Daniel; PALMA, José Carlos Sant'anna; MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar. Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. In: DATE, 2003, Munique, Germany, p. 1122-1123.

PALMA, José Carlos Sant'anna; MELLO, Aline Vieira de; MÖLLER, Leandro Heleno; MORAES, Fernando Gehm; CALAZANS, Ney Laert Vilar. Core Communication Interface for FPGAs. In: SBCCI, 2002, Porto Alegre, Brazil, p. 183-188.

MÖLLER, Leandro Heleno; MESQUITA, Daniel; MORAES, Fernando Gehm. Tool-Set for Remote and Partial Reconfiguration. In: SIM, 2002, Gramado, Brazil, p. 127-130.

MESQUITA, Daniel; MORAES, Fernando Gehm; PALMA, José Carlos Sant'anna; MÖLLER, Leandro Heleno; CALAZANS, Ney Laert Vilar. Reconfiguração Parcial e Remota de Cores FPGAs. In: IBERCHIP, 2001, Montevideo, Uruguay (in portuguese).

MÖLLER, Leandro Heleno. Ferramentas de Reconfiguração Total, Parcial e Remota de Dispositivos FPGA Virtex. In: II Salão De Iniciação Científica, 2001, Porto Alegre, Brazil (in portuguese).

Betreute Vorlesungen und Praktika:

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