Faizal Arya Samman

Wissenschaftliche und Berufliche Ausbildung:

1991 – 1994 : SMA Negeri Sungguminasa, Gowa, Indonesien (Naturwissenschaftliches Abitur)

1994 – 1999 : Universitas Gadjah Mada (UGM), Yogyakarta, Indonesien (Bachelor)

2000 – 2002 : Institut Teknologi Bandung (ITB), Indonesien (Master)

2006 – 2010 : Technische Universität Darmstadt, Promotion mit DAAD-Stipendium (Doktor-Ingenieur)

2010 – jetzt : Wissenschaftlicher Mitarbeiter (Post-Doktorand) an der TU Darmstadt.

Laufende Projekte:

  • Projekt AdRIA (Adaptronic – Research, Innovation, Application) in Zusammenarbeit mit Fraunhofer Institut für Betriebsfestigkeit und Systemzuverlässigkeit (LBF) im LOEWE-Zentrum AdRIA.
  • Projekt MoDe (Maintenance on Demand) im Rahmen des europäischen Forschungs- und Entwicklungsprogramms FP7 (Seventh Framework Programme).
  • Projekt FAIR (Facility for Antiproton and Ion Research) in Zusammenarbeit mit dem GSI Helmholtzzentrum für Schwerionenforschung.

Forschungs- und Arbeitsbereiche:

  • Wireless Sensor Networks – Platform and Protocol Design
  • Power-Management for Micropower Energy Harvesting Systems
  • Low Power Application-Specific Processors
  • Accelerator-based Parallel Computing for Many-Core Processor Systems
  • Electronic Signal Processing for Sensor Systems
  • Adaptive und Robust Control Systems for Adaptronic Applications

Journal-Veröffentlichungen:

  • F. A. Samman, T. Hollstein, M. Glesner. „Wormhole Cut-Through Switching: Flit-Level Messages Interleaving for Virtual-Channelless Network-on-Chip“, Elsevier Journal, Microprocessors and Microsystems, vol. 35, no. 3, pp. 343-358, May 2011 (doi:10.1016/j.micpro.2011.01.003, ISSN:0141-9331).
  • F. A. Samman, T. Hollstein, M. Glesner. „New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip“, IEEE Trans. on Parallel and Distributed Systems, vol. 22, no. 4, pp. 544-557, April 2011 (doi:10.1109/TPDS.2010.120, ISSN:1045-9219).
  • F. A. Samman, T. Hollstein, M. Glesner. „Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip“, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, pp. 1067-1080, July 2010 (doi:10.1109/TVLSI.2009.2019758, ISSN:1063-8210).
  • F. A. Samman, T. Hollstein, M. Glesner. „Networks-on-Chip based on Dynamic Wormhole Packet Identity Management“, VLSI Design, Journal of Hindawi Pub., vol. 2009, Article ID 941701, pp. 1-15, Jan. 2009 (doi:10.1155/2009/941701, ISSN:1065514X).

Konferenz und Tagungsbände:

  • F. A. Samman, P. Surapong, C. Spies and M. Glesner. „Floating-point-based Hardware Accelerator of a Beam Phase-Magnitude Detector and Filter for a Beam Phase Control System in a Heavy-Ion Synchrotron Application“, in Proc. of the 13th Int'l Conf. on Accelerator and Large Experimental Physics Control Systems (ICALEPCS 2011), Grenoble, France, 10-14 Oct. 2011.
  • F. A. Samman and M. Glesner. „Adaptive Digital Signal Processor based on Floating Point Units for Rapid Prototyping of Electronic Units in Adaptronic Systems“, in Proc. of the Mikrosystemtechnik-Kongress (MST 2011), Darmstadt, Germany, 10-12 Oct. 2011.
  • F. A. Samman and M. Glesner. „Architecture and Components of Adaptive Control Signal Processors based on Floating-Point Arithmetic for Adaptronic Applications“, in Proc. of the Adaptronic Congress 2011 (AC 2011), Darmstadt, Germany, 7-8 Sept. 2011.
  • F. A. Samman, P. Surapong and M. Glesner. „Reconfigurable Streaming Processor Core with Interconnected Floating-Point Arithmetic Units for Multicore Adaptive Signal Processing Systems“, in Proc. the 6th Int'l Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2011), Montpellier, France, 20-22 June 2011.
  • T. Hollstein, F. A. Samman, A. Jaiswal, H. Ying, M. Glesner and K. Hofmann. „Design Criteria for Dependable System-on-Chip Architectures“, in Proc. the 6th Int'l Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2011), Montpellier, France, 20-22 June 2011.
  • F. Philipp, F. A. Samman and M. Glesner, „Design of an Autonomous Platform for Distributed Sensing-Actuating Systems“, in Proc. of the 22nd IEEE Symp. on Rapid System Prototyping (RSP 2011), Karlsruhe, Germany, 24-27 May 2011.
  • F. Philipp, F. A. Samman and M. Glesner, „Real-time Characterization of Noise Sources with Computationally Optimised Wireless Sensor Networks“, in Proc. of the 37th Annual Convention for Acoustics (Deutsche Jahrestagung für Akustik, DAGA 2011), Düsseldorf, Germany, March 21-24, 2011.
  • F. Philipp, P. Zhao, F. A. Samman and M. Glesner, „Demonstration: Monitoring and Control of a Dynamically Reconfigurable Wireless Sensor Node Powered by Hybrid Energy Harvesting“, in Design, Automation & Test in Europe (DATE 2011), University Booth, Grenoble, France, March 14-18, 2011.
  • F. A. Samman, F. Philipp and M. Glesner. „Reconfigurable Interconnect Infrastructure for Multi-FPGA-based Adaptive Multiprocessing Systems“, in Proc. of the 16th ACM Int'l. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2011), Workshop on Computing in Heterogeneous, Autonomous and Goal-oriented Environments (CHA'N'GE 2011), Newport Beach, California, USA, March 5-11, 2011.
  • H. Ying, A. Jaiswal, T. Hollstein, F. A. Samman and K. Hofmann. „Fault Tolerant Interface and Fault Injection Model for Networks-on-Chip“in Proc. the 23th GI/GMM/ITG Workshop on Test Methods and Reliability of Circuits and Systems (Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, TUZ 2011), Passau, Germany, Feb. 27-March 1, 2011.
  • F. A. Samman, T. Hollstein, M. Glesner. „Test Strategy for Network-on-Chip Supporting Unicast-Multicast Data Transport“, Workshop of Diagnostic Services in Network on Chips (DSNoC'09), in conjunction with Design Automation and Test in Europe (DATE'09) Conference and Exhibition, Nice, France, 20-24 April 2009.
  • F. A. Samman, T. Hollstein, M. Glesner. „Planar Adaptive Router Microarchitecture for Tree-based Multicast Network-on-Chip“, in Proc. of the 41st Annual IEEE/ACM Int'l Symposium on Microarchitecture (MICRO-41), Network on Chip Architecture Workshop (NoCArch'08), Como, Italy, 8-12 Nov. 2008.
  • F. A. Samman, T. Hollstein, M. Glesner. „Flexible Infrastructure for Network-on-Chip Prototypes Development based on VHDL-Modular-Oriented Design“, in Proc. of the 11th Indonesian Student's Scientific Meeting (ISSM'08), Delft, The Netherlands, 13-15 May 2008.
  • F. A. Samman, T. Hollstein, M. Glesner. „Network-on-Chips: Potential Synergy between Parallel Computing and Multicore Processor Systems“, in Proc. of the 11th Indonesian Student's Scientific Meeting (ISSM'08), Delft, The Netherlands, 13-15 May 2008.
  • F. A. Samman, T. Hollstein, M. Glesner. „NoCs with combined low and high priority wormhole packet delivery services“, in Proc. of the 2nd Electronic Design Automation Workshop (edaWorkshop'08), Hannover, Germany, 6-7 May 2008.
  • F. A. Samman, T. Hollstein, M. Glesner. „Flexible Parallel Pipeline Network-on-Chip Based on Dynamic Packet Identity Management“, in Proc. of the 22nd IEEE Int'l Conference on Parallel and Distributed Processing Symposium (IPDPS'08), Reconfigurable Architecture Workshop (RAW'08), Miami Florida, USA, 14-15 April 2008.
  • F. A. Samman, T. Hollstein, M. Glesner. „Multicast Parallel Pipeline Router Architecture for Network-on-Chip“, in Proc. of Design Automation and Test in Europe (DATE'08) Conference and Exhibition, Munich, Germany, 10-14 March 2008.

Offene Arbeiten

18.10.2011

Offene Studien-, Bachelor-, Master-, Diplomarbeit

Modelling and Simulation of heterogeneous subsystems in adaptronic applications.

Heterogeneous subsystems such as Laplace and Z-transfer functions, ADC, Low-Pass Filter, Digital Circuit Core, DAC, Sample-Hold circuit, Power Amplifier circuit, etc will be modelled by using VHDL-AMS (Analog/Mixed-Signal). VHDL-AMS is an advanced hardware description language standardized by IEEE, which can be used to model heterogeneous systems such as difference and differential equations, linear and non linear system models, analog and digital circuits, etc. Each subsystem will be independently modelled as a modular cell or component. The interactions between the components will be simulated and observed by using AMS Designer tools from Cadence. In this topic, Student who has interest will gain an advanced skill to model heterogeneous systems and to simulate mixed analog-digital systems.

Detail in PDF-file

18.10.2011

Offene Studien-, Bachelor-, Master-, Diplomarbeit

Design and Implementation of Wallace-TreeMultiplier.

A 32-bit Wallace-Tree Digital Multiplier will be designed and simulated by using VHDL or Verilog HDL. The Multiplier is one of important components that will be used to implement a high-performance pipeline floating-point (FP) multiplier. The critical path of the FP multiplier is located in the multiplication stage. There are some techniques that can be used to realize a digital multiplier suchas Wallace-Tree method. This method is famous and enables us to pipeline the multiplication process in order to shorten the critical path. The performance and logicarea of the Wallace-Tree Multiplier will be analysed by using Design Vision tool fromSynopsys.

Detail in PDF-file

18.10.2011

Offene Studien-, Bachelor-, Master-, Diplomarbeit

Modelling and Simulation of heterogeneous systems in energy harvesting applications.

Heterogeneous subsystems such as ADC, Low-Pass Filter, Digital Circuit Core, DAC, Sample-Hold circuit, PWM Circuit, etc will be designed by using VHDL-AMS (Analog/Mixed-Signal). VHDL-AMS is an advanced hardware description language standardized by IEEE, which can be used to model heterogeneous systems such as difference and differential equations, linear and non linear system models, analog and digital circuits, etc. Each subsystem will be independently modelled as a modular cell or component. The interactions between the components will be simulated and observed by using AMS Designer tools from Cadence. In this topic, Student who has interest will gain an advanced skill to model heterogeneous systems and to simulate mixed analog-digital systems.

Detail in PDF-file

18.10.2011

Offene Studien-, Bachelor-, Master-, Diplomarbeit

Design and Implementation of Floating-Point Square Root, Division, Logarithmic and Exponent Functions.

Beside basic operations such as adding, subtracting and multiplication, there are also arithmetic operations such as square root, division, logarithmic, exponent function, etc, which are used to perform computing algorithms in a scientific computing application. There are some methods that can be used to implement the operations such as CORDIC (COordinateRotation DIgitalComputer) method. A challenge to implement an IP core of the functions by using VHDL or Verilog HDL based on floating-point data format is proposed. Student who has interest can select one of the function units, which he/she prefers to design. The performance and logic areaof the selected function will be analysed by using Design Visiontool from Synopsys.

Detail in PDF-file

18.10.2011

Offene Studien-, Bachelor-, Master-, Diplomarbeit

Analog/Mixed-Signal IP Cores Design: CMOS multiplier, subtractor, low pass filter, ADC.

In the frame of the Project LOEWE-AdRIA (Adaptronik-Research, Innovation, Application), we are offering a Bachelor/Master Thesis or (Studien-/Diplomarbeit) about IP core design of an analog multiplier, subtractor and low pass filter, which are used in an ambient energy harvesting system. The cores will be integrated together with a PWM-Circuit for a solar-based and/or a TEG-based energy-harvesting system, which is an important part for battery-powered wireless sensor network applications.

Detail in PDF-file

18.10.2011

Offene Studien-, Bachelor-, Master-, Diplomarbeit

Floating-Point to DAC-Input Signal Converter and ADC Output to Floating-Point Converter Circuit.

Converter circuits will be designed and implemented by using VHDL or Verilog HDL. One converter is designed to transform the output signals of a floating-point digital signal processor into binary signals that can be read by a DAC circuit. The other other converter is designed to transform the output signals of an ADC circuit into floating-point binary signals that can be processed further by a floating-point digital signal processor. The format of the floating-point data is in accordance with IEEE Std 754-2008, i.e. 32-bit (single precision) with 1 sign bit + 8 exponent bits + 23 mantissa bits. A simple method such as two-point regression method can be used to realize an IP core of the converters. The converters are important parts of a floating-point-based application-specific processor for embedded applications. Student who has interest can select one of the converter circuits, which he/she prefers to design.

Detail in PDF-file

 

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Mitgliedschaft: Mitglied bei IEEE, ACM, VDI/VDE