Location :

The Workshop will take place in the building S3|20 of the TU Darmstadt (Rundeturmstraße 10). You will find instructions on how to get there on this page

Wednesday, July 10th 2013

Time Talk
08:30 – 09:00 Registration
09:00 – 09:15 Welcome Addresses
Manfred Glesner (TU Darmstadt), General Chair
Gert Jervan (Tallinn University of Technology) and Alberto Garcia Ortiz (University of Bremen), Program Chairs
09:15 – 10:15 Keynote 1
Some Design Issues for 3D NoCs : From Circuits to Systems
Frédéric Piétrot (TIMA Lab, Grenoble)
Chair : Gert Jervan (Tallinn University of Technology) and Alberto Garcia Ortiz (University of Bremen)
10:15 – 10:45 Coffee break
10:45 – 12:00 Session 1 : Dynamic Reconfiguration
Chair : Manfred Glesner (TU Darmstadt)
  Dynamically Reconfigurable FIR Filter Architectures with Fast Reconfiguration
Martin Kumm, Konrad Möller and Peter Zipf (University of Kassel)
  An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture
Vianney Lapotre (Université de Bretagne Sud), Michael Huebner (Ruhr-Universität Bochum), Guy Gogniat (Université de Bretagne Sud), Purushotham Murugappa, Amer Baghdadi (TELECOM Bretagne) and Jean-Philippe Diguet (Université de Bretagne Sud).
  Simulation Framework for Cycle-Accurate RTL Modeling of Partial Run-Time Reconfiguration in VHDL
Simen Gimle Hansen, Dirk Koch and Jim Torresen (University of Oslo).
12:00 – 13:30 Lunch break
13:30 – 14:45 Special Session : Architectures and development for application specific processors
Chair : Diana Göhringer (Ruhr-Universität Bochum)
  CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design
Juan Eusse, Christopher Williams and Rainer Leupers (RWTH Aachen).
  SoC Performance Evaluation with ArchC and TLM-2.0
Jörg Walter, Jörg Lenhardt and Wolfram Schiffmann (University of Hagen).
  Register Allocation for High-Level Synthesis of Hardware Accelerators Targeting FPGAs
Gerald Hempel, Jan Hoyer, Thilo Pionteck (TU Dresden) and Christian Hochberger (TU Darmstadt).
14:45 – 15:00 Poster Introductions (2 min / Poster)
Chair : François Philipp
15:00 – 15:30 Coffee break / Poster Session
15:30 – 17:10 Session 2 : Networks-on-Chip
Chair : Thomas Hollstein (Tallinn University of Technology)
  Centralized Traffic Monitoring for online-resizable Clusters in Networks-on-Chip
Philipp Gorski and Dirk Timmermann (Universität Rostock).
  Improving Parallel MPSoC Simulation Performance by Exploiting Dynamic Routing Delay Prediction
Christoph Roth, Harald Bucher, Simon Reder, Oliver Sander and Juergen Becker (KIT).
  Measuring Memory Access Latency for Software Objects in a NUMA System-on-Chip Architecture
Daniela Genius (LIP6, Paris)
  Dynamic Task Remapping For Power and Latency Performance Improvement In Priority-Based Non-Preemptive Networks On Chip
James Harbin and Leandro Indrusiak (University of York).
  Social Event
Guided tour by Brigitte Kuntzsch Along the cultural axis : from Darmstadt Castle to Mathildenhöhe
Finger Food Buffet (Building S3|20)

Thursday, July 11th 2013

Time Talk
08:45 – 10:30 Keynote 2
Targeting Applications and Platform “Variability” Challenges: The barbecueRTRM approach
William Fornaciari (Politecnico di Milano)

Keynote 3

Template-based design and programming of self-adaptive architectures for embedded systems
Jean-Philippe Diguet(Lab-STICC, CNRS, UMR 6285)

Chair : Leandro Soares Indrusiak (University of York)
10:30 – 11:00 Coffee break / Poster Session
11:00 – 13:05 Special Session : Reconfigurable Systems for Security Applications
Chair : *Steffen Reith (Hochschule RheinMain)
*Replacing Marc Stöttinger
  Among Slow Dwarfs and Fast Giants: A Systematic Design Space Exploration of Keccak
Bernhard Jungk (easycore GmbH) and Marc Stöttinger (Nanyang Technological University, Singapore).
  A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m
Eduardo Cuevas-Farfan (INAOE), Miguel Morales-Sandoval (CINVESTAV), René Cumplido, Claudia Feregrino-Uribe (INAOE) and Ignacio Algredo-Badillo (University of Istmo).
  Exploiting FPGA block memories for protected cryptographic implementations
Shivam Bhasin (TELECOM ParisTech), Wei He (Universidad Politécnica de Madrid), Sylvain Guilley (GET/ENST) and Jean-Luc Danger (TELECOM ParisTech).
  On a FPGA-based Method for Authentication using Edwards Curves
Andre Himmighofen, Bernhard Jungk (easycore GmbH) and Steffen Reith (Hochschule RheinMain).
  A New Model for Estimating Bit Error Probabilities of Ring-Oscillator PUFs
Matthias Hiller, Georg Sigl and Michael Pehl (TU München).
13:05 – 14:30 Lunch break
14:30 – 15:20 Session 3 : Architectures
Chair : Thilo Pionteck (TU Dresden)
  ACMA: Accuracy-Configurable Multiplier Architecture for Error-Resilient System-on-Chip
Kartikeya Bhardwaj and Pravin S Mane (BITS Pilani – Goa).
  Flexible, Ultra-Low Power Sensor Nodes through Configurable Finite State Machines
Juan Carlos Pena Ramos and Marian Verhelst (KU Leuven).
15:20 – 16:10 Session 4 : Design Flows
Chair : Diana Göhringer (Ruhr-Universität Bochum)
  An FPGA Design and Implementation Framework Combined with Commercial VLSI CADs
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi (Kumamoto University).
  A Framework for Effective Exploitation of Partial Reconfiguration in Dataflow Computing
Riccardo Cattaneo, Christian Pilato, Marco Domenico Santambrogio (Politecno di Milano), Xinyu Niu, Tobias Becker, and Wayne Luk (Imperial College).
16:10 – 16:30 Coffee break
16:30 – 17:45 Session 5 : System-Level design and HW/SW Co-design
Chair : Dominic Hillenbrand (Waseda University)
  The HeartBeat model: a platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA
Francesco Robino and Johnny Öberg (KTH Stockholm).
  Memory Allocation and Optimization in System-Level Architectural Synthesis
Shuo Li and Ahmed Hemani (KTH Stockholm).
  Hardware/Software Co-Compilation with the Nymble Compiler
Jens Huthmann, Björn Liebig, Julian Oppermann and Andreas Koch (TU Darmstadt).
19:00 Social Event :
Dinner at Bayrischer Hof Darmstadt

Friday, July 12th 2013

Time Talk
08:45 – 10:15 Keynote 3:
Efficiency Metrics and Bandwidth– A Memory Perspective
Norbert Wehn (TU Kaiserslautern)

Keynote 4:
Design of Energy-Aware Cyber-Physical Systems
Christoph Grimm (TU Kaiserslautern)

Chair : Gilles Sassatelli (LIRMM, Montpellier)
10:15 – 10:35 Coffee Break
10:35 – 11:25 Session 6 : Energy Efficiency
Chair : Peter Zipf (University of Kassel)
  Reconciling Application Power Control and Operating Systems for Optimal Power and Performance
Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Mikami Hiroki, Keiji Kimura and Hironori Kasahara (Waseda University).
  Energy-Aware Dynamic Reconfiguration of Communication-Centric Applications for Reliable MPSoCs
Anup Das, Amit Singh and Akash Kumar (National University of Singapore).
11:25 – 12:40 Special Session : Architecture, programming and run-time techniques for heterogeneous MPSoCs
Chair : Luciano Ost (LIRMM, Montpellier)
  Component Based Design using Constraint Programming for Module Placement on FPGAs
Alexander Wold, Dirk Koch and Jim Torresen (University of Oslo).
  An Exploration of Heterogeneous Systems
Jesús Carabaño, Francisco Dios, Masoud Daneshtalab and Masoumeh Ebrahimi (University of Turku).
12:40 – 14:00 Lunch break
14:00 – … Glesner Honorary Colloquium (70th Birthday)

Addiguration: Exploring configuration behavior of Spartan-3 devices
Michael Dreschmann, Oliver Sander, Alexander Klimm, Christoph Roth and Juergen Becker (KIT).
Bitfile Preservation – Generation Of Reusable Out Of Context Modules
Christian Stuellein, Norbert Abel and Udo Kebschull (Goethe-University Frankfurt).
Approximation of Hyperbolic Tangent Activation Function Using Hybrid Methods
Maicon Sartin (UNEMAT) and Alexandre C. R. Silva (UNESP).
A parallelization methodology for reconfigurable systems applied to edge detection
Juan M Campos, Rene Cumplido, Claudia Feregrino (INAOE) and Jose Roberto Perez Andrade (CINVESTAV).
RecMIN: a Reconfiguration Architecture for Network on Chip
Alexander Logvinenko, Carsten Gremzow and Dietmar Tutsch (University of Wuppertal).
Towards a Configurable Many-core Accelerator for FPGA-based Embedded Systems
Marco Ramirez, Masoud Daneshtalab, Pasi Liljeberg and Juha Plosila (University of Turku).
Shared Hardware Accelerator Architectures for Heterogeneous MPSoCs
Bouthaina Dammak (UHVC), Mouna Baklouti (ENIS), Smail Niar (UHVC) and Mohamed Abid (ENIS).
D-RECS: A Complete Methodology to Implement Self Dynamic Reconfigurable FPGA-Based Systems
Fabio Cancare, Christian Pilato, Andrea Cazzaniga, Donatella Sciuto and Marco Domenico Santambrogio (Politecnico di Milano).
Practical measurements of data path delays for IP authentication & integrity verification
Ingrid Exurville, Jacques Fournier, Jean-Max Dutertre, Bruno Robisson and Assia Tria (ENSMSE).